-- $Id: $
-- File name:   tb_SHIFT_REG.vhd
-- Created:     10/5/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Test Bench

library ieee;
--library gold_lib;   --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all;   --UNCOMMENT if you're using a GOLD model

entity tb_SHIFT_REG is
generic (Period : Time := 83.34 ns);
end tb_SHIFT_REG;

architecture TEST of tb_SHIFT_REG is

  function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
     return STD_LOGIC_VECTOR is
    variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
    variable tmp : INTEGER;
  begin
    tmp := X;
    for i in 0 to NumBits-1 loop
      if (tmp mod 2)=1 then
        res(i) := '1';
      else
        res(i) := '0';
      end if;
      tmp := tmp/2;
    end loop;
    return res;
  end;

  component SHIFT_REG
    PORT(
         CLK : in std_logic;
         RST_N : in std_logic;
         SHIFT_ENABLE : in std_logic;
         D_ORIG : in std_logic;
         RCV_DATA : out std_logic_vector (7 downto 0)
    );
  end component;

-- Insert signals Declarations here
  signal CLK : std_logic;
  signal RST_N : std_logic;
  signal SHIFT_ENABLE : std_logic;
  signal D_ORIG : std_logic;
  signal RCV_DATA : std_logic_vector (7 downto 0);

-- signal <name> : <type>;

begin

CLKGEN: process
  variable CLK_tmp: std_logic := '0';
begin
  CLK_tmp := not CLK_tmp;
  CLK <= CLK_tmp;
  wait for Period/2;
end process;

  DUT: SHIFT_REG port map(
                CLK => CLK,
                RST_N => RST_N,
                SHIFT_ENABLE => SHIFT_ENABLE,
                D_ORIG => D_ORIG,
                RCV_DATA => RCV_DATA
                );

--   GOLD: <GOLD_NAME> port map(<put mappings here>);

process

  begin

-- Insert TEST BENCH Code Here
    RST_N <= '1';
    wait for 2*period;

    RST_N <= '0';
    wait for 2*period;

    D_ORIG <= '1';
    SHIFT_ENABLE <='0';
    wait for period;
    RST_N <= '1';
    wait for period;
    SHIFT_ENABLE <='1';
    wait for period;


--??????????????????????
--     SHIFT_ENABLE <='0';
--     wait for 80 ns;
-- 
--     SHIFT_ENABLE <='1';
--     wait for 80 ns;
--??????????????????????
--     --data to be sent in 1010 0011
--     D_ORIG <= '1';
--     wait for 83.34 ns;
--     D_ORIG <= '1';
--     wait for 83.34 ns;
--     D_ORIG <= '0';
--     wait for 83.34 ns;
--     D_ORIG <= '0';
--     wait for 83.34 ns;
--     D_ORIG <= '0';
--     wait for 83.34 ns;
--     D_ORIG <= '1';
--     wait for 83.34 ns;
--     D_ORIG <= '0';
--     wait for 83.34 ns;
--     D_ORIG <= '1';


    --data to be sent in 1010 0101
    D_ORIG <= '1';
    SHIFT_ENABLE <='0';
    wait for period;
    D_ORIG <= '0';
    wait for period;
    D_ORIG <= '1';
    wait for period;
    D_ORIG <= '0';
    wait for period;

    SHIFT_ENABLE <='1';

    D_ORIG <= '0';
    wait for period;
    SHIFT_ENABLE <='0';
    D_ORIG <= '1';
    wait for period;
    D_ORIG <= '0';
    wait for period;

    SHIFT_ENABLE <='1';
    D_ORIG <= '1';


    wait for 4*period;
    RST_N <= '0';
    SHIFT_ENABLE <='0';
    wait;
-- 
-- 
-- --?????????????????????????
-- --?????????????????????????
--     wait for 100 ns;
--     RST_N <= '1';
--     SHIFT_ENABLE <='1';
--     wait for 80 ns;
--     --data to be sent in 1111 1111
--     D_ORIG <= '1';
--     wait for 40 ns;
--     D_ORIG <= '1';
--     wait for 80 ns;
--     D_ORIG <= '1';
--     wait for 80 ns;
--     D_ORIG <= '1';
--     wait for 80 ns;
-- 
--     D_ORIG <= '1';
--     wait for 80 ns;
--     D_ORIG <= '1';
--     wait for 80 ns;
--     D_ORIG <= '1';
--     wait for 80 ns;
--     D_ORIG <= '1';
-- 
-- 
-- 
-- 
-- 
--     wait for 100 ns;
--     RST_N <= '0';
--     SHIFT_ENABLE <='0';
--     --wait;
--     wait for 100 ns;
--     RST_N <= '1';
--     SHIFT_ENABLE <='1';
--     wait for 80 ns;
--     wait for 100 ns;
-- 
--     --data to be sent in 0000 0000
--     D_ORIG <= '0';
--     wait for 40 ns;
--     D_ORIG <= '0';
--     wait for 80 ns;
--     D_ORIG <= '0';
--     wait for 80 ns;
--     D_ORIG <= '0';
--     wait for 80 ns;
-- 
--     D_ORIG <= '0';
--     wait for 80 ns;
--     D_ORIG <= '0';
--     wait for 80 ns;
--     D_ORIG <= '0';
--     wait for 80 ns;
--     D_ORIG <= '0';








  end process;
end TEST;